Methods involving memory with high dielectric constant antifuses adapted for use at low voltage

ABSTRACT

Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective.

REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/367,258, filed Feb. 6, 2009, now U.S. Pat. No. 8,314,023, which is adivision of U.S. patent application Ser. No. 11/173,973, filed Jul. 1,2005. This application relates to U.S. patent application Ser. No.11/174,234 by N. Johan Knall, titled “REVERSE-BIAS METHOD FOR WRITINGMEMORY CELLS IN A MEMORY ARRAY”; and to U.S. patent application Ser. No.11/174,240, by James M. Cleeves, titled “MEMORY CELL WITH HIGH-KANTIFUSE FOR REVERSE BIAS PROGRAMMING”; each of which also was filed onJul. 1, 2005, and is incorporated herein by reference in its entirety.

BACKGROUND

The invention relates to programming and reading an array of nonvolatilememory cells each comprising a diode in series with an antifuse.

Integrated circuit memories are typically large arrays of memory cellsconnected between bit lines and word lines. In order to achieve reliableprogramming and reading of the memory cells within the array, memorycells selected to be programmed or read must be isolated from memorycells that are not selected. Also, as it becomes increasingly importantto minimize power used by integrated circuit devices, it is desirable tominimize power consumption in integrated circuit memories. Lowering thevoltage for reading and writing usually reduces power consumption. Alsolowering the voltage usually allows elements of the integrated circuitdevice to shrink, thus reducing manufacturing cost. Therefore it isdesirable to program and operate memories at lower voltages.

FIG. 1 shows a representative portion of an integrated circuit memoryarray in which voltages have been applied in order to program one of thememory cells. Each of the memory cells comprises a diode in series withan antifuse connected between one of the word lines and one of the bitlines in the memory array. In FIG. 1, the cell selected to be programmedis at the intersection of word line WL4 and bit line BL2. To programthis cell, a high voltage of 9 volts is applied to word line WL4 and aground voltage of 0 volts is applied to bit line BL2, thus applying 9volts to selected cell 4,2 at this intersection.

To avoid programming any of the other unselected cells, other bit linesreceive a voltage of 8.5 volts and other word lines receive 0.5 volts.This causes all unselected cells, for example cell 1,1 to receive areverse bias voltage (in the reverse direction of normal current flowthrough the diode) of −8.0 volts. Half-selected cells (in which eitherthe word line or the bit line receives a selected voltage) receive aforward bias voltage of 0.5 volts, which is less than the thresholdvoltage of the diodes, so only a small amount of current flows throughthe half-selected cells.

To avoid reverse bias breakdown, the diodes must be manufactured so thatthey can tolerate the reverse bias of 8 volts, and the antifuses must bemanufactured to be somewhat leaky so that most of the voltage drop isacross the diode and not the antifuse to assure that this relativelyhigh voltage does not cause programming of the antifuse in unselectedcells. However, during programming, the reverse leakage through theunselected cells causes power drain. In a large array having manyunselected memory cells, this power drain can be considerable.

For example, in a two-dimensional array of 1000×1000 memory cells, thereare one million memory cells. If only one row and one bit line areselected, there are 999×999 unselected cells all receiving an 8-voltbias, producing considerable power drain through the array. It isdesirable to minimize power drain, and particularly important tominimize power drain in battery operated applications. It is alsodesirable to shrink the area occupied by the memory array, therebyreducing cost.

Other materials besides silicon and silicon dioxide have been consideredfor making some integrated circuit structures. FIG. 2 a, taken from IEDMDecember 2002 paper number 26.6 by J. McPherson, et al., titled“Proposed Universal Relationship Between Dielectric Breakdown andDielectric Constant,” shows measured values of dielectric constant andbreakdown strength for about 10 materials and shows that the correlationcoefficient between dielectric constant and breakdown strength is about0.81, which indicates a high correlation between the two parameters.

A paper by Joe W. McPherson, et al., titled “Trends in the UltimateBreakdown Strength of High Dielectric-Constant Materials,” published inIEEE Transactions on Electron Devices, Vol. 50, No. 8, August 2003,indicates that the ultimate breakdown strength E_(bd) of a dielectricmaterial is found to decrease as the dielectric constant K increases.The paper indicates that great interest exists in the breakdown strengthof high-K dielectrics because for CMOS technology scaling to continue,the conventional SiO₂ gate-dielectric (which has a high E_(bd)) must bereplaced. The paper gives new time-dependent dielectric breakdown (TDDB)data over a wide range of dielectric materials. The paper also discussesacceleration factor (the relationship between voltage and time tobreakdown) and gives acceleration factor data for selected materials.But the McPherson et al. paper says nothing about materials used formaking antifuses or diodes such as are used for making memory cells.

FIG. 2 b, taken from the August 2003 paper by Joe W. McPherson, et al.,also examines breakdown strengths of four materials: silicon dioxide(SiO₂), hafnium silicon oxynitride (HfSiON), tantalum oxide (Ta₂O₅), andPZT (a lead zirconate titanate ceramic), as a function of dielectricconstant. (FIGS. 2 a and 2 b have a different appearance, but that ismainly because FIG. 2 a uses log-log scales and FIG. 2 b uses linearscales.)

SUMMARY

The present invention is defined by the appended claims, and nothing inthis section should be taken as a limitation on those claims. Ingeneral, the invention is directed to methods of forming and programmingan array of nonvolatile memory cells each comprising an antifuse inseries with a diode. The invention takes advantage of the one-way natureof the diode and uses materials that allow for lower voltage operation.In particular, antifuses having dielectric constants higher than that ofsilicon dioxide and diodes having band gaps lower than that of siliconare found to be effective in allowing the memories to operate at lowervoltages.

To shrink the memory cell horizontal area without having manufacturingproblems, the vertical dimension of the memory cell must also bereduced, and that means the write voltage and read voltage must bereduced. But antifuses and diodes made from films of silicon dioxidehave already been made just a few atoms thick, and cannot be madethinner. However, using a material with a higher dielectric constantallows films of dielectric to be thicker for the same breakdown fieldstrength (breakdown voltage divided by thickness is breakdown fieldstrength).

One aspect of the invention is to form a memory cell from a diode inseries with an antifuse where the antifuse is made, not from silicondioxide, but from a material having a higher dielectric constant thansilicon dioxide. The elements lanthanum (La), hafnium (Hf), tantalum(Ta), yttrium (Y), zirconium (Zr), and niobium (Nb) when oxidized orcombined with nitrogen form dielectrics with higher dielectric constantsthan silicon dioxide and can each be used to form antifuses in memorycells that can be written and read at lower voltages than silicondioxide.

An aspect of the invention is to assure that the dielectric constant ofthe insulator used for the memory cell antifuse is higher than that ofsilicon dioxide (3.9). In particular, a dielectric constant range ofapproximately 5 to 27 in the antifuse and a band gap smaller than thatof silicon work well to produce memory cells that can be reliably readand written at lower voltages than memory cells of silicon dioxide andsilicon.

When the antifuse is formed from an insulator having a dielectricconstant above about 5 and the diode is a thin film with a band gapsmaller than silicon, the memory cells can be programmed by applying alow voltage in a direction opposite that of natural current flow throughthe diode, which shorts the antifuse to produce the programmed memorycell. A programming voltage sufficient to short the antifuse can belower than that required to program a memory cell made from a silicondioxide antifuse and a doped silicon diode. While a selected memory cellis being programmed, unselected memory cells preferably receive minimalvoltage, thus minimizing power consumption in the memory array.

It is also advantageous to program such a memory cell by applying twovoltages in the forward direction of the diode. The first application ofvoltage shorts the antifuse (forms a conductive path through theantifuse), and the second application of voltage makes a larger openingat the location of the short, thus reducing resistance to current flowthrough the short location.

It is important to avoid disturbing or programming unselected memorycells while programming the selected cells. It is also important toavoid disturbing any of the memory cells while reading the memory cells,and this is true for the life of the device, which may be on the orderof 10 years. A memory cell array is accessed by word lines and bitlines, typically running orthogonal to each other in separate horizontallayers of an integrated circuit structure, such that each memory cell isaccessed by one word line and one bit line. The memory cells of thepresent invention each comprise an antifuse in series with a diode. Theantifuse may be placed at either the cathode end or the anode end of thediode.

According to one aspect of the invention, while a voltage sufficient toshort an antifuse is applied to a bit line contacting the selectedmemory cell and a ground voltage is applied to a word line contactingthe selected memory cell, a voltage less than or equal to the diodethreshold voltage is applied to bit lines of unselected cells and avoltage that is lower than the voltage sufficient to short an antifuseof a memory cell by one diode threshold voltage is applied to word linescontacting unselected memory cells. This assures that the selectedmemory cell is programmed and that unselected memory cells are notprogrammed or otherwise disturbed.

BRIEF DESCRIPTION OF THE DRAWINGS

Features of the present invention can be more clearly understood fromthe following detailed description considered in conjunction with thefollowing drawings, in which the same reference numerals denote the sameelements throughout.

FIG. 1 is a memory array showing prior art programming voltages.

FIG. 2 a shows breakdown strength as a function of dielectric constantfor a range of materials usable in semiconductor devices.

FIG. 2 b shows another curve of breakdown strength as a function ofdielectric constant.

FIGS. 3 a and 3 b shows an exemplary physical structure of memory cellelements comprising a diode plus an antifuse in a three-dimensionalarray.

FIG. 4 shows voltage versus current curves for some programmed andunprogrammed memory cells in exemplary devices.

FIG. 5 shows voltage versus current curves similar to those of FIG. 4but in which the height of a memory cell has been reduced.

FIG. 6 shows four curves of acceleration factor, which istime-to-breakdown as a function of electric field strength.

FIG. 7 shows a table of dielectric constant, acceleration factor, andbreakdown strength for several materials usable in the manufacture ofintegrated circuit memory arrays.

FIG. 8 shows voltages that can be used for programming memory cellsaccording to the invention.

FIG. 9 shows voltages that can be used for reading memory cellsaccording to the invention.

FIG. 10 shows voltages that can be used for writing memory cells withreverse bias, according to another embodiment of the invention.

DETAILED DESCRIPTION

When developing improvements in integrated circuit memories, it isdesirable to reduce the cost of manufacturing while improving operatingspeed, reducing power consumption, and maintaining a good usefullifetime of the devices. The present invention is directed to memoryarrays in which memory cells are formed from a diode and an antifuseconnected in series. Preferred embodiments orient the diode and antifusein a vertical stack between word lines and bit lines.

A critical requirement for shrinking memory devices to deep submicronsizes is to reduce the voltage levels required to write and read thememory cells. For example, whereas the prior art programming voltageillustrated in FIG. 1 is about 9 volts, the present invention will allowprogramming in the range of 3 to 5 volts. Read voltage can similarly bereduced to about 1 to 1.5 volts. Reducing the required read and writevoltages of the memory cells also allows shorter channel length CMOSdevices to be used in support circuits.

When the write voltage is reduced in the diode-plus-antifuse memorycells of the invention, the length of the intrinsic or lightly dopedregion between the heavily doped n+ and p+ portions of the diode can bereduced. Thus, a shorter vertical diode can be used in the memory cell.The horizontal spacing between memory cells can be reduced as thevertical diode is reduced in height, which further reduces the area ofthe memory array.

This area reduction and voltage reduction reduces cost and powerconsumption. The lower write voltage is particularly important for thediode-plus-antifuse memory cells of this invention because leakagecurrents in the large number of unselected memory cells iscorrespondingly reduced by reducing voltage applied to the unselectedcells.

Careful attention to several parameters of materials used in the memorycells is especially important to reduce the write and read voltagesapplied to diode-plus-antifuse memory arrays and especially formonolithic three-dimensional memory arrays. A monolithic threedimensional memory array is one in which multiple memory levels areformed above a single substrate, such as a wafer, with no interveningsubstrates. The layers forming one memory level are deposited or growndirectly over the layers of an existing level or levels.

In contrast, stacked memories have been constructed by forming memorylevels on separate substrates and adhering the memory levels atop eachother, as in Leedy, U.S. Pat. No. 5,915,167, “THREE DIMENSIONALSTRUCTURE MEMORY.” The substrates of stacked memories may be thinned orremoved from the memory levels before bonding, but since the memorylevels are initially formed over separate substrates, such memories arenot true monolithic three dimensional memory arrays.

FIGS. 3 a and 3 b illustrate the structure of two embodiments of theinvention. The diode is made up of a P layer on top of an N− layer ontop of an N+ layer. In FIG. 3 a, this diode sits on an antifuse, whichsits on a word line WL. A bit line runs horizontally in a firstdirection above the diode structure. The word line WL runs horizontallyin a second direction below the antifuse structure. Thus, the antifuseis at the cathode end 100 of the diode and is positioned between thecathode end 100 of the diode and the cathode end 110 of the entirememory cell.

In FIG. 3 b, the structure is similar except that the P layer of thediode is adjacent the antifuse and therefore the antifuse is between theanode end 200 of the diode and the anode end 210 of the memory cell. Inanother embodiment not shown, the antifuse is positioned between the Player of the diode and the N layers of the diode. The invention canincorporate any desired diode plus antifuse arrangement. The memory cellwill be described as having a cathode end 110 and an anode end 210 eventhough an antifuse may be between the end of the diode and the end ofthe memory cell.

Further information about manufacturing diodes useful with the presentinvention can be found in:

-   -   Herner and Dunton, U.S. patent application Ser. No. 11/125,606,        titled “HIGH-DENSITY NONVOLATILE MEMORY ARRAY FABRICATED AT LOW        TEMPERATURE COMPRISING SEMICONDUCTOR DIODES,” filed May 9, 2005,        and    -   Herner and Walker, U.S. patent application Ser. No. 10/954,577,        titled “JUNCTION DIODE COMPRISING VARYING SEMICONDUCTOR        COMPOSITIONS,” filed Sep. 29, 2004.

Suitable memory cell structures and configurations useful forcross-point antifuse arrays include, without limitation, those describedin the following enumerated disclosures, each of which is incorporatedherein by reference in its entirety:

-   -   Johnson, et al., U.S. Pat. No. 6,034,882, titled “VERTICALLY        STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF        FABRICATION”;    -   Knall, et al., U.S. Pat. No. 6,420,215, titled        “THREE-DIMENSIONAL MEMORY ARRAY AND METHOD OF FABRICATION”;    -   Johnson, U.S. Pat. No. 6,525,953, titled “VERTICALLY-STACKED,        FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF        FABRICATION”;    -   Cleeves, U.S. patent application Ser. No. 10/185,508, filed Jun.        27, 2002, titled “THREE DIMENSIONAL MEMORY”;    -   Herner, et al., U.S. patent application Ser. No. 10/326,470,        filed Dec. 19, 2002, titled “AN IMPROVED METHOD FOR MAKING A        HIGH DENSITY NONVOLATILE MEMORY”; and    -   Herner, et al., U.S. patent application Ser. No. 11/015,824,        titled “NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT        VERTICAL DIODE,” filed Dec. 17, 2004.

FIGS. 4 and 5 show voltage versus current curves for exemplary devices.FIG. 4 shows the current to voltage characteristic curves of are-crystallized silicon diode-plus-antifuse memory cell incorporating avertical diode with a height of 350 nanometers. FIG. 5 shows thecharacteristic curves of a similar cell incorporating a vertical diodewith a height of 220 nanometers. The invention is envisioned with diodesthat are even shorter.

Some embodiments of the invention incorporate low band gap materialssuch as a silicon germanium alloy or even a pure germanium semiconductoras the low bandgap material. Examples of such diodes for incorporationin the memory cell are described in more detail in the followingreferences, each of which is incorporated in its entirety herein byreference:

-   -   Herner, et al., U.S. patent application Ser. No. 10/326,470,        supra;    -   Petti, et al., U.S. patent application Ser. No. 10/728,230,        “SEMICONDUCTOR DEVICE INCLUDING JUNCTION DIODE CONTACTING        CONTACT-ANTIFUSE UNIT COMPRISING SILICIDE,” filed Dec. 3, 2003;        and    -   Herner, et al., U.S. patent application Ser. No. 10/954,577,        “JUNCTION DIODE COMPRISING VARYING SEMICONDUCTOR COMPOSITIONS,”        filed Sep. 29, 2004.

It is desirable to reduce the height of vertical memory cell structuresin order to reduce gaps formed as the structures are being patterned andfilled with a dielectric. Deep gaps are difficult to fill withoutleaving voids that can cause manufacturing and reliability problems. Themaximum aspect ratio that can be used without defects is determined bythe manufacturing equipment.

Thus, using a tall memory cell limits reducing the spacing betweenmemory cells and thereby the density of the memory cells. In oneembodiment, this invention incorporates shorter vertical diodesdescribed in previously listed U.S. patent application Ser. No.11/015,824. However, in this previous structure, an unintendedprogramming problem may occur.

As shown in FIG. 4 for the memory cell with a 350 nanometer diode, anunprogrammed memory cell exhibits a current versus voltage curveindicated by short dashed lines and labeled “Unprogrammed.” For thereverse biased direction shown at the left side of the figure, currentremains small until voltage in the reverse direction exceeds about 10volts.

Thus, unprogrammed memory cells will not carry large current when areverse bias is applied at voltages below about 10 volts. This isimportant when programming voltages indicated by FIG. 1 are applied,since the large number of unselected cells all experience a relativelylarge reverse bias of about 8 volts.

Returning to FIG. 4, when some of the memory cells have been programmed(their antifuses have been shorted), their voltage versus current curvesare indicated by long dashed lines labeled “Programmed.” The reversebias current rises sharply at about 10 volts but may still be acceptableat a reverse bias of 8 volts.

However, the curves of FIG. 5 for memory cells with a 250 nanometerthick diode show a less favorable picture. Reverse bias current is highbut possibly acceptable for unprogrammed cells, but for programmedcells, indicated by the long dashed lines labeled “Programmed,” currentrises sharply at a reverse bias of about 8 volts, and a large number ofpreviously programmed cells will cause the memory array to experience anunacceptable current during attempts to program other cells. Because ofthis, it is unacceptable to provide and program memory cells havingshort silicon diodes and silicon dioxide antifuses that must receive theprogramming voltages indicated in FIG. 1.

One solution to this problem has been discussed in U.S. patentapplication Ser. No. 11/174,234 of N. Johan Knall, titled “REVERSE-BIASMETHOD FOR WRITING MEMORY CELLS IN A MEMORY ARRAY.” That patentapplication previously has been incorporated herein by reference.Another solution to the problem is to replace the silicon and silicondioxide materials used in the antifuses and diodes with differentmaterials having different breakdown strengths, different thicknesses,different dielectric constants, different acceleration factors (seebelow) and different band gaps.

Breakdown Strength

In order to program at lower voltage without making the antifuse toothin, the antifuse material must have a lower breakdown strength at anadequate thickness. Recent measurements of breakdown strength (theelectric field strength at which the dielectric develops a sudden andsustained rise in leakage current) as a function of dielectric constantsof materials have shown that there is a negative correlation betweenbreakdown strength E_(bd) and dielectric constant K. Silicon dioxide(SiO₂) has a dielectric constant of 3.9 and a breakdown strength ofabout 13 MV/cm (megavolts per centimeter).

Higher-K dielectrics break down at lower field strengths, and thereforelower voltages for the same thickness. For optimum benefit, someembodiments incorporate a combination of changes. For antifuses, amaterial with a higher dielectric constant than silicon dioxide is usedat a greater thickness than commonly used for silicon dioxide antifusessuch that the change in dielectric constant is greater than the changein thickness. Hence a lower breakdown voltage is achieved along withgreater manufacturing ability for the antifuse.

Antifuse Thickness

It is desirable to make antifuses with a thickness greater than 20angstroms. If antifuse thickness becomes less than 20 angstroms (only afew atoms thick), rather than simply breaking down at a correspondinglylower voltage, another phenomenon occurs. Below about 20 angstroms, uponapplication of a voltage, the dielectric exhibits high tunneling currentwithout breaking down, such that it is difficult to form a permanentconductive path.

An antifuse should behave as an insulator until a breakdown voltage isreached, then develop a permanent conductive path due to melting in thepresence of high current that occurs upon breakdown. Therefore it isdesirable to use antifuse materials that have sufficiently highdielectric constants that they can be made thicker than 20 angstroms andstill break down cleanly at a fairly low voltage.

Making the antifuse too thick also has problems. Increased thicknessincreases resistance (reduces leakage) through the antifuse to the pointthat voltage drop across the memory cell (antifuse plus diode) is almostentirely across the antifuse, and the diode no longer protects theantifuse sufficiently from being shorted when a reverse bias is appliedto the memory cell. Therefore, it is undesirable to use antifusematerials that have such a high dielectric constant that they must bemade thicker than about 65 angstroms. We have found that a thicknessrange of 20 to 65 angstroms avoids both these problems.

Antifuse Materials

Some of the materials indicated in FIG. 2 a have dielectric constantsappropriate for antifuse manufacture. It is desirable to use a materialwith dielectric constant more than about 5 and less than about 27. Ifthe dielectric constant is much lower than 5 (as with silicon dioxide),the voltage needed to break down the thinnest practical antifuse will betoo high to allow the low voltage operation that accompanies furthershrinkage-of the memory array. If the dielectric constant is much higherthan 27, the leakage is too large to maintain a long read lifetime, orthe material must be too thick to break and form a low resistance paththrough the memory cell.

Also, a thickness greater than about 65 angstroms interferes with a goodaspect ratio for maintaining good step coverage during manufacturing.Thus materials used in the invention have a dielectric constant betweenabout 5 and about 27. Materials used in the invention are manufacturedto have a thickness of 20 to 65 angstroms.

Materials that appear satisfactory for making antifuses programmable atlower voltages can be described with the general formulasX_(v)Si_(w)O_(x), X_(v)O_(w) and X_(v)Si_(w)O_(x)N_(y), where Xrepresents an element from the family consisting of lanthanum (La),hafnium (Hf), tantalum (Ta), yttrium (Y), zirconium (Zr), and niobium(Nb) and the subscripts v, w, x, and y can have any value that forms astable compound. Thus, some acceptable materials include HfO₂, La₂O₃,LaSiON, Hf₂SiO, HfSiON, Ta₂O₅, Ta₂O₃N to name a few.

Acceleration Factor

For both easy writing and undisturbed reading, it is desirable to have amaterial that sharply changes its behavior in response to changing theapplied voltage. That is, when being written at a WRITE voltage, thematerial should break down and change states quickly, for example over aperiod of microseconds or less in order for the memory cell to bewritten. However, when being read at a somewhat lower READ voltage, thematerial should reliably not break down even over an extended lifetimeon the order of 10 years.

Thus, for a desirable material, a curve that relates time to breakdownto voltage should have a steep slope. This slope is called accelerationfactor. We have recognized that a high acceleration factor is beneficialin the manufacture and operation of integrated circuit memory cells thatuse antifuses. Thus we have examined materials looking for highacceleration factors, thinking such materials could be used to makeantifuses and diodes in memory cells.

As presented in the above McPherson et al. paper, the characteristicbreakdown strengths E_(bd) of SiO₂, HfSiON, Ta₂O₅, and PZT are 13.6, 7,4, and 0.8 MV/cm, respectively. However, even though the breakdownstrength E_(bd) is observed to decrease with dielectric constant K, thefield acceleration factor γ is observed to increase with K. We see thatE_(bd) decreases as approximately K^(−0.65), while γ increases asK^(0.66). For high-K materials, the field acceleration factor γ issignificantly greater than that for SiO₂.

Desirable Antifuse Characteristics

FIG. 6 shows empirical results for four materials described in theMcPherson et al. paper, including silicon dioxide for comparison.Silicon dioxide has an acceleration factor γ of 3.5 cm/MV. This meansthat time to breakdown decreases moderately as voltage is increased. Butin order to achieve a sufficiently short write delay, a very high writefield strength (off the scale of FIG. 6) must be applied.

To achieve this high field strength, the programming voltage must bevery large, even when the silicon dioxide antifuse is made as thin asfeasible in manufacturing. For the thinnest feasible silicon dioxidethickness, the minimum write voltage for reasonable write performance isabout 7 volts, which is higher than desired for scaling the memory arraysupport circuits below a 300 nanometer gate length. Other materials giveimproved results. Other materials have a higher dependence on voltage,as indicated by the steeper curves.

The next curve in FIG. 6 is for hafnium silicon oxynitride, HfSiON. Thismaterial has a steeper acceleration factor γ of 6.5 cm/MV and abreakdown field strength E_(bd) of 7 MV/cm. The steepness of the HfSiONcurve means that writing can be done quickly at a 38 angstrom thickness,and reading may be done at 1.5 volts, which leaves a lifetime of thememory cells in the acceptable 10-year range.

The acceleration factor curves of FIG. 6 suggest a method that can beused to select materials with optimum antifuse characteristics regardingthickness and dielectric constant that satisfy requirements for lifetimeand operating voltage in an antifuse memory array. Because of thestraight line shape of the acceleration factor curves and the inverseexponential relationship between E_(bd) and γ, as described above, allthe lines in FIG. 6 will converge at a point far above the data rangeshown.

The line equations all have the form “y=mx+b”, where the slope “m”depends on K but not thickness, and the intercepts “b” are all the same.The desired read lifetime and write lifetime are labeled on horizontallines in FIG. 6. There are similar lines for other materials that extendfrom the intercept b through the read lifetime to the write lifetime.For each of these materials, the ratio of field strength E at the readlifetime to field strength E at the write lifetime is about 46%.

One aspect of the present invention is to use a read voltage that isless than about 46% of the write voltage. In one embodiment, the readvoltage is between 0.8 volts and 1.5 volts. A material is chosen thathas a dielectric constant in the range of 5 to 27. Setting the readfield strength to be 46% of the write field strength determines anoptimum thickness. For the material HfSiON, for example, the read fieldstrength can be seen to be 4 MV/cm, which establishes an antifusethickness of 38 angstroms for a read voltage of 1.5 volts.

Similarly, if tantalum oxide Ta₂O₅ at the high end of the desired Krange, is selected, the desired read field strength is 2.4 MV/cm, and athickness of 63 angstroms, at the top end of the desired thickness rangeis needed in order to assure the 10-year lifetime during reading.

But another material, PZT, has such a steep acceleration curve andbreaks down at such low field strength that this material would have tobe 400 angstroms thick to be read at 1.5 volts over a long lifetime, soPZT is not practical for antifuses in memory cells that will be read at1.5 volts. Of course, the same methodology can be used to choose amaterial and an optimum thickness and dielectric constant if a higher orlower read voltage is desired. For a higher or lower read voltage, theoptimum material would have a correspondingly lower or higher dielectricconstant.

Additional materials are practical for antifuse use. FIG. 7 shows atable of characteristics of some materials being considered for use inmemories. In particular, the elements lanthanum (La), hafnium (Hf),tantalum (Ta), yttrium (Y), zirconium (Zr), praseodymium (Pr), titanium(Ti), and niobium (Nb) can all form oxides (La₂O₃, HfO₂, Ta₂O₅, Y₂O₃,ZrO₂, Pr₂O₃, TiO₂, Nb₂O₅) having higher dielectric constants and lowerbreaking strength than silicon dioxide (SiO₂).

Other compounds and alloys, in particular, HfON, are also beneficial.Silicon has been found to improve temperature stability on transitionmetal oxides, and can be partially substituted for the transitionmetals. In this case, the ratio of the metal to silicon can be variedover a wide range.

Lower Band Gap Materials for Diodes

When considering materials for the diode of the memory cell, the bandgap of the diode material must be considered. It is a further aspect ofthe invention that the read voltage is reduced by using a low bandgapsemiconductor material to form the diode. Band gap is an intrinsicproperty of a material, and determines the threshold voltage of thediode and to some extent the conductivity through the diode. The bandgap of silicon is about 1.12 electron volts at 300 degrees Kelvin. Theread voltage using re-crystallized silicon diodes has been about 2volts.

At lower sensing currents, the read voltage for a silicon diode coulddrop a few hundred millivolts, but it is difficult to form a silicondiode that can be read reliably at 1.5 volts. It is desirable to formthe diodes from a material with a lower band gap than that of silicon sothat programming of antifuses in series with the diodes may be done morequickly and at lower programming voltages. Lifetime of the antifuses inthe array is especially improved by using a lower read voltage becausefor the one-time-programmable memory cells of this invention, far moreof the lifetime is spent in read operations.

One group of materials that works well for diodes is the groupconsisting of germanium and the silicon germanium alloys. The diodes maybe formed either by re-crystallizing or by depositing the selected diodematerial.

The general formula Si_(x)Ge_(1-x) encompasses this family of materials(though elemental silicon is not included).

As germanium content increases, the band gap decreases proportionally to0.66 electron volts for pure germanium. So pure germanium has about halfthe diode threshold voltage of pure silicon. This Si_(x)Ge_(1-x) familyis useful for reducing the required read voltage while retainingadequate current, and allows read voltage to be reduced by half a voltor more. Gallium antimony has a band gap of 0.72 electron volts and isalso suitable for diodes. Indium arsenic at 0.36 electron volts and leadsulfide at 0.41 electron volts can provide even lower acceptable readvoltages.

Programming and Reading

With the new materials discussed above, it is possible to quicklyprogram (write) memory cells using forward diode bias voltages to thememory cells that are lower than used in the prior art. It is alsopossible to read the memory cells without disturbing their values over along lifetime, expected to be on the order of 10 years.

FIG. 8 shows application of voltages for writing a selected memory cell.It is easy to see by comparing FIG. 8 to FIG. 1 that all voltage levelsare lower. By selecting thickness and dielectric constant of the diodesand antifuses, the back bias voltages across the memory cells (in FIG.8, −4 volts) can be predominantly across the diode of the memory cell,especially if the antifuse has been previously programmed, so that nounintended programming occurs.

In one embodiment, two successive programming voltages are applied. Thefirst voltage shorts the antifuse to form a conductive path and thesecond voltage causes current to pass through the shorted antifuse andfurther reduces resistance of the shorted antifuse. In one embodiment,the first voltage is chosen to provide the desired write field and thesubsequent current through the antifuse is not well controlled due tothe very sudden pop event.

The second voltage is about two volts higher at the array line driver,and is provided through a current limiting circuit such as any well knowcurrent mirror circuit. The current limit is adjusted to give a usefulrange of programmed cell resistance values, but the voltage at eachmemory cell is less well controlled due to variation in location alongthe array lines, which have inherent resistance drops.

FIG. 9 shows application of voltages for reading a selected memory cell.As can be seen in FIG. 9, the selected cell receives a forward readvoltage of 1.5 volts, the half-selected cells receive zero volts, andthe unselected cells receive a reverse bias of −1.5 volts. Thesevoltages are low enough that no programming of unselected orhalf-selected cells occurs, and yet voltage to the selected cell (whichmay be a row or multi-layer stack of selected cells) is sufficient todetermine the state of the antifuse in the selected cell.

In one embodiment using an antifuse material of hafnium siliconoxynitride in a layer 38 angstroms thick, the READ voltage applied tothe selected cell is 1.5 volts. If the cell has been programmed, currentflowing from the word line WL4 to bit line BL2 is about 1 microamp,while if the cell has not been programmed, the current is about 1nanoamp. Thus the state of this memory cell can be observed.

Reverse bias voltage applied to unselected cells is −1.5 volts, which islow enough to produce negligible leakage current. Bias to half-selectedcells is 0 volts, which produces no current. In another embodiment notshown, the diodes are reversed to connect the anodes to the bit lines.During reading, the selected word line is at ground voltage, theselected bit line is current-sensed and clamped at a voltage of 1.5volts. The unselected word lines are at 1.5 volts, and the unselectedbit lines are at ground voltage. Thus all cells experience the samevoltage drop as those shown in FIG. 9.

FIG. 10 shows another application of voltages for writing a selectedmemory cell. In FIG. 10, voltages are applied to reverse bias theselected cell. The biasing arrangement of FIG. 10 experiences very lowleakage because all unselected cells receive zero bias. The benefits ofreverse biasing are further described in Knall, U.S. patent applicationSer. No. 11/174,234. The smaller voltage values of FIG. 10, however, areachieved by using the materials discussed above.

Thus the selection of new materials discussed above allows programmingand reading at lower voltages than the prior art. Because the devicescan be scaled to smaller dimensions, both power and cost ofmanufacturing are reduced.

A word line arrangement having multiple layers of word line segments forthree-dimensional memory arrays may be used with memory cells of thepresent invention. Such a word line arrangement is described by Roy E.Scheuerlein in detail in U.S. patent application Ser. No. 10/403,844,which is incorporated herein by reference in its entirety. A method forsensing while programming a non-volatile memory cell described byKleveland, et al., in U.S. Pat. No. 6,574,145, may be used with thepresent invention for sensing memory cell values, and is incorporatedherein by reference in its entirety.

The foregoing detail has described only a few of the many possibleimplementations of the present invention. For this reason, this detaileddescription is intended to illustrate, not to limit. Variations andmodifications of the embodiments disclosed herein may be made based onthe description set forth herein, without departing from the scope andspirit of the invention. It is only the following claims, including allequivalents, that are intended to define the scope of this invention.

While certain embodiments have been described in the context of athree-dimensional, field-programmable, memory array, it should beappreciated that such an array is not necessarily required. Moreover,the embodiments described above are specifically contemplated to be usedalone as well as in various combinations. Accordingly, otherembodiments, variations, and improvements not described herein are notnecessarily excluded from the scope of the invention.

1. A method of programming an array of memory cells each comprising anantifuse in series with a diode, each antifuse comprising an insulatorhaving a dielectric constant above 5, each diode comprising a thin filmsemiconductor material with a band gap smaller than that of silicon, themethod comprising: programming a selected one of the memory cells byapplying a first voltage in a direction opposite that of natural currentflow through the diode of the selected memory cell, the first voltagebeing sufficient to short the antifuse.
 2. The method of claim 1,further comprising: applying a second voltage to word lines contactingunselected ones of the memory cells; and applying a third voltage to bitlines contacting the unselected ones of the memory cells, wherein thesecond and third voltages are substantially equal.
 3. The method ofclaim 2, wherein the second and third voltages are approximately halfthe first voltage applied to the selected one of the memory cells.
 4. Amethod of programming a memory cell comprising an antifuse in serieswith a diode, the antifuse comprising an insulator having a dielectricconstant above 5, the diode comprising a semiconductor material having aband gap smaller than that of silicon, the method comprising: applying afirst voltage in a direction of natural current flow through the diode,the first voltage being sufficient to short the antifuse; and applying asecond voltage in the direction of natural current flow through thediode, the second voltage being sufficient to cause current to passthrough the shorted antifuse and to further reduce resistance of theshorted antifuse.
 5. The method of claim 4, wherein the memory cell is aselected cell within an array of memory cells each contacting a bit lineat its cathode end and a word line at its anode end, the method furthercomprising: applying the first voltage to a word line contacting theselected memory cell; applying a third voltage to word lines contactingunselected memory cells, wherein the third voltage is lower than thefirst voltage and above zero; and applying a fourth voltage to bit linescontacting unselected memory cells, wherein the third voltage is lowerthan the first voltage and above zero.
 6. The method of claim 5, whereinthe third voltage is less than or equal to a threshold voltage of diodesin the memory cells.
 7. The method of claim 4, wherein the secondvoltage is greater than the first voltage.
 8. The method of claim 4,wherein the second voltage is less than the first voltage.
 9. A methodof forming a memory cell, the method comprising: forming a diode; andforming a resistance-switching material layer coupled in series with thediode, wherein the resistance-switching material layer: (a) has adielectric constant in the range of about 5 to about 27, and (b)comprises a material from the family consisting of X_(v)O_(w), wherein Xrepresents an element from the family consisting of Hf and Zr, andwherein the subscripts v and w have non-zero values that form a stablecompound.
 10. The method of claim 9, wherein the diode comprises a bandgap smaller than 1.12 electron volts.
 11. The method of claim 9, whereinthe diode comprises one or more of germanium (Ge) and a silicongermanium alloy (Si_(x)Ge_(1-x)).
 12. The method of claim 9, wherein theresistance-switching material layer has a thickness between 20 and 65angstroms.
 13. The method of claim 9, wherein the resistance-switchingmaterial layer comprises HfO₂ or ZrO₂.
 14. The method of claim 9,wherein the memory cell is adapted to be programmed with a voltage lessthan about 5 volts.
 15. The method of claim 9, wherein the diodecomprises re-crystallized material.
 16. The method of claim 9, whereinforming the diode comprises depositing semiconductor material.
 17. Themethod of claim 9, wherein the diode is adapted to be read using a biasvoltage less than about 2 volts.
 18. The method of claim 9, furthercomprising forming an array of the memory cells.
 19. The method of claim9, further comprising forming a monolithic 3-dimensional array of thememory cells.